1. Field of the Invention
The invention relates to forming a semiconductor structure, more particularly for forming a semiconductor structure having a deep sub-micron line-width.
2. Description of the Prior Art
The semiconductor technology right now is still highly researched and developed to improve the current semiconductor device performance; also, deep sub-micron scale or so-called nano-scale line-width metal electrode technology is a key technology for semiconductor device manufacturing and could become much more important when the device dimension continues being downscaled. The previous sub-micron scale line-width metal electrode technology all can be carried out by the photolithography technology. However, forming deep sub-micron scale or so-called nano scale metal electrode using conventional photolithography technology is more challenging.
At the present day, for deep sub-micron technology development, optical lithography combined with the Phase-Shift Mask (PSM), extreme ultraviolet lithography (EUVL) or electron-beam Lithography (EBL) all can be used for the exposure process with the main purpose of shrinking down the line-width. Nevertheless, the investment cost of the hardware equipment, maintenance or materials will be highly increased. In addition, for EBL, the throughput is an issue that may become practical concern for the industrial mass production. As a result, technologies targeting deep sub-micron or nano scale resolution without using any expensive phase-shift mask or advanced lithography equipments are indispensably required for reducing production cost.
For high-frequency applications, device having sub-micron or nanometer gate with mushroom cross-section will be necessary. The mushroom gate is with small footprint for a short gate length and with large cross-sectional area in the top for lower gate resistance. This can simultaneously avoid parasitic resistances and achieve better performance at high frequencies. A wide variety of mushroom type gates including T, Γ, or Y shaped gates have been demonstrated successfully to improve device performances at microwave or millimeter-wave frequencies.
About the photolithography technology related principium in the semiconductor field, photoresist mask for protecting the underneath semiconductor from etching or ion implanted will be firstly defined and formed, and then selectively etching step or implantation step will be proceeded.
Normally, the character of photoresist under lighting will be changed due to the light energy. For positive photoresist, after being exposed, the bonding of the positive photoresist will be interrupted, then the positive photoresist will be solved under the develop step. The un-exposed portion of the positive photoresist will be retained, as the acid-resisting armor layer. For the negative photoresist, after the negative photoresist under being exposed, the bonding of the negative photoresist will be connected, then the negative photoresist will be retained under the develop step. The un-exposed portion of the negative photoresist will be solved.
Furthermore, for better understanding of prior techniques related to sub-micron or deep sub-micron gate patterning, efforts were made to carry out literature study and patent search. Related prior arts are described and discussed in the followings:
In U.S. Pat. No. 4,532,698, “Method of making ultrashort FET using oblique angle metal deposition and ion implantation”, multiple tilt-angle metal evaporation steps and multiple etching steps are performed to remove the residual surface metal. However, it is not easy to control the line-width and the overall process is quit complex. Furthermore, it is not easy to realize T-type or Γ-type gate formation by this technique.
In U.S. Pat. No. 4,687,730, “Lift-off technique for producing metal pattern using single photoresist processing and oblique angle metal deposition”, the method only used a single layer of photoresist and partially development was carried out to form photoresist groove. Partially development is not easy to control when compared to the selective development in the multi-layer resist structure. Furthermore, it is not easy to realize T-type or Γ-type gate formation by this technique. The overall process is relatively simple when compared to the present advanced technology. However, its application still would be quite limited.
In U.S. Pat. No. 5,652,179, “Method of fabricating sub-micron gate electrode by angle and direct evaporation”, vertical anisotropic etching process and multiple metal evaporations, including twice tilt-angle metal evaporation steps and a vertical metal evaporation step, were used. Finally, the assisted metal pattern has to be removed. Although Γ type gate with sub-micron line-width can be formed, the process steps are more complex. The method disclosed in this invention is time-consuming and with higher production cost.
Therefore, new technology with simple process steps, lower production cost and sub-micron line-width capability will be urgently required as the time cost or performance factors are essential considerations for mass production in semiconductor industry.